▼BB68
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bb68
bb68-word
bb68-gpr
bb68-ccc
bb68-gprp
bb68-msw
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1 Core Definitions🔗

 (require ledum/bb68/defs) package: ledum-bb68

value

bb68 : isa0?

A 16-bit ISA defined using define-isa.

syntax class

bb68-word

A syntax class matching a 16-bit integer.

Dream CPU (again) "The proper things, in the proper manner, in the proper order. God help us all." – Cultist Simulator

Goals and philosophy

* doable even with relatively crude tools * easy to program in assembly, allowing for bootstrapping * complete and easy to understand instruction set * instruction timing reasonably easy to predict

value

bb68-gpr : ent0?

Characters: r, m, n

Bits required: 4

Element:

r0

r1

r2

r3

r4

r5

r6

r7

r8

r9

ra

rb

rc

rd

re

rf

Encoding:

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Entity documentation comes here.

value

bb68-ccc : ent0?

Characters: c

Bits required: 3

Element:

N

Z

C

S

A

NZ

NC

NS

Encoding:

0

1

2

3

4

5

6

7

value

bb68-gprp : ent0?

Characters: R, M, N

Bits required: 3

Element:

r01

r23

r45

r67

r89

rab

rcd

ref

Encoding:

0

1

2

3

4

5

6

7

GPRP – General Purpose Register Pairs.

The ordering of the registers in the pair is as in the following example for register pair r01:

Register: 

r0

r1

Register bit: 

15

14 .. 1

0

15

14 .. 1

0

Pair bit: 

31

30 .. 17

16

15

14 .. 1

0

value

bb68-msw : ent0?

Characters: s

Bits required: 6

Element:

%isa

%emcf

%escr0

%escr1

%evecs

%evecp

%erets

%eretp

%MSW8

%MSW9

%MSW10

%MSW11

%MSW12

%MSW13

%MSW14

%MSW15

%MSW16

%MSW17

%MSW18

%MSW19

%MSW20

%MSW21

%MSW22

%MSW23

%MSW24

%MSW25

%MSW26

%MSW27

%MSW28

%MSW29

%MSW30

%MSW31

%MSW32

%MSW33

%MSW34

%MSW35

%MSW36

%MSW37

%MSW38

%MSW39

%MSW40

%MSW41

%MSW42

%MSW43

%MSW44

%MSW45

%MSW46

%MSW47

%MSW48

%MSW49

%MSW50

%MSW51

%MSW52

%MSW53

%MSW54

%MSW55

%MSW56

%MSW57

%MSW58

%MSW59

%MSW60

%MSW61

%MSW62

%MSW63

Encoding:

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

Machine status words

%isa machine information (16 bit bit mask, as yet unspecified)

%emcf “exception mask cause flags” – this register is split into fields. The lowest nibble contains the original values of Z flag at bit 1, C flag at bit 2, and S flag at bit 3. The bit 0 is reset for traps and set for external interrupts. The bits 7:5 specify the exception cause: in the external interrupt it is the interrupt number 0-7, in trap case it is the trap kind enumeration value. The bit 4 is always set in an exception handler and serves as a global interrupt disable bit. The bits 15:8 are the mask, where 1 = disabled interrupt.

%escr0 and %escr1 are two scratch registers with no CPU enforced meaning. They are usually used in the exception handler to save some registers.

%evecs and %evecp exception segment and pointer registers. The cs:cp is set to this value on interrupt/trap.

%erets and %eretp exception segment and pointer return address registers. The cs:cp is set to this value of the instruction to resume after interrupt/trap.

FIXME: Easy for the interrupt: this is the address of the as yet unexecuted instruction that was due at the time the interrupt arrivrd. Decide if the address of the offending instruction is stored in the trap case or the instruction after that. Think of current/next PC values in the HW implementation.

For trap this is set to the instruction that caused the trap. If you emulate the errorneous instruction you need to adjust those values to skip the offending instruction.

Other MSW registers are unspecified.

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